1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a highly integrated semiconductor device with improved reliability.
2. Discussion of the Related Art
Generally, as the packing density of an integrated circuit increases, the device size decreases and its metal line becomes finer and multilevel. Accordingly, the step coverage on a contact hole, a via hole or an uneven surface of the device becomes more important. To solve this problem in a dynamic random access memory (DRAM), a self aligned contact hole was proposed. This contact hole is formed in such a manner that double insulating layers are formed, and its lower insulating layer is not etched when a hole is formed in its upper insulating layer.
The conventional method of fabricating a semiconductor device employing the self aligned contact hole is disclosed in U.S. Pat. No. 5,384,287 and will be explained below with reference to FIGS. 1A to 1G. As shown in FIG. 1A, on a semiconductor substrate 1 including a cell region and a periphery region, a field oxide layer 2 for isolating devices from each other is formed on a field region of the semiconductor substrate 1. An active region is defined by the field oxide layer 2, i.e., where the field oxide layer 2 is not formed. Thereafter, a first insulating layer 3, a polysilicon layer 4 and a second insulating layer 5 are sequentially formed on the overall surface of the substrate 1.
Referring to FIG. 1B, a first photoresist layer (not shown) is formed on the second insulating layer 5, and selectively exposed and developed to form a first photoresist pattern (not shown). Then, the second insulating layer 5, the polysilicon layer 4 and the first insulating layer 3 are selectively removed using the first photoresist pattern as a mask, to thereby form gate electrodes. Here, the first insulating layer 3 is used as a gate insulating layer, and the second insulating layer is used as a cap gate insulating layer. The second insulating layer may be formed of nitride. Thereafter, impurity ions are implanted in a lower concentration into the substrate 1 using the gate electrodes as a mask, to thereby form a lightly doped impurity region. A third insulating layer is formed on the substrate 1 including the gate electrodes and etched back, to thereby form gate sidewalls 6 on both sides of the gate electrodes. Then, impurity ions are implanted in a higher concentration into the substrate 1 using the gate electrodes, the sidewalls 6 and a second photoresist pattern (not shown) which selectively masks the cell region as a mask, to thereby form source and drain impurity regions 7 having a lightly doped drain (LDD) structure only on the periphery region. The second and third insulating layers are to serve as a lower insulating layer when a self aligned contact hole is formed in the following process.
Referring to FIG. 1C, a fourth insulating layer 9 is formed on the overall surface of the substrate, and a third photoresist layer is formed thereon. Here, the fourth insulating layer 9 serving as an interlevel insulating layer may be formed of an oxide.
Referring to FIG. 1D, the third photoresist layer is selectively exposed and developed to thereby form a third photoresist pattern 10 defining a contact hole region. This contact hole region is defined only in the periphery region.
Referring to FIG. 1E, the fourth insulating layer 9 and the second insulating layer 5 are selectively etched using the third photoresist pattern 10 as a mask. By doing so, contact holes 11 and 11a are formed to respectively expose a predetermined portion of the substrate 1, and the surface of the gate electrodes.
Here, the actual areas of the contact holes formed through the etching of the fourth insulating layer 9 are smaller than the areas defined by the third photoresist pattern 10. This is because the sidewall 6 formed on the side of the gate electrode reduces the area of the contact hole.
Referring to FIG. 1F, a fourth photoresist layer 10a is formed on the overall surface of the substrate 1 including the fourth insulating layer 9, and only a portion of the fourth photoresist layer 10a placed on the cell region is selectively exposed and developed, thereby forming a fourth photoresist pattern 10a.
Referring to FIG. 1G, the fourth insulating layer 9 is selectively etched using the fourth photoresist pattern 10a as a mask, to thereby expose a predetermined portion of the substrate. By doing so, contact holes are formed. Thereafter, a metal layer is formed on the overall surface of the substrate including the contact holes and selectively etched through photolithography, to thereby form a metal line 12.
The aforementioned conventional method of fabricating a semiconductor device has the following problems. First, the surface of the substrate in the periphery region is overetched when the cap gate insulating layer, i.e., the second insulating layer, is etched because the cap gate insulating layer and the interlevel insulating layer (i.e., the fourth insulating layer) have etch selectivity to each other. This leads to poor quality of the contact hole pattern on the source and drain regions. As a result, the characteristic of the device is deteriorated. In addition, since the contact holes in the periphery region and the cell region are patterned using separate photoresist patterns, it is difficult to have accurate alignment.